Computing devices such as, but not limited to, mobile computing devices, may comprise one processor, or CPU, for processing high level Operating System (OS) operations and end-user application operations, and a second CPU for processing modem operations. These processors are often referred to as the applications processor (AP) and the baseband processor or modem processor (MP), respectively. In such an architecture, the AP and MP often communicate through the use of a high speed interface adapted to support very high data rates. One type of high speed interface is an SDIO interface.
One SDIO interface comprises an architecture having an asymmetric communication protocol between an AP Secure Digital Card Controller (SDCC) host and an MP SDIO client, with all data transfers being initiated and controlled by the SDCC host. The use of the SDIO interface as an interconnect between the AP and the MP poses special challenges for supporting very high data rates. For example, when IP packets must be transferred between the processors, not an insignificant portion of the data transfer between the processors comprises protocol overhead such as, but not limited to, control information.
For example, a single SDIO transfer of data typically requires initiation of a CMD 53 operation from the SDCC host in order to read data to, or write data from, the SDCC host. The CMD 53 operation may specify a number of bytes (or a number of blocks, with each block comprising a pre-configured size, such as, 256 bytes) to read from, or write to, the SDIO client. Each CMD 53 command may be followed by a data transfer phase in which the data blocks/bytes are read from the SDIO client, or written to the SDIO client. Typically, a SDIO transfer may be initiated for each IP packet, with a typical maximum packet size corresponding to an Ethernet Maximum Transmission Unit (MTU) of about 1500 bytes.
Therefore, SDIO control data may be attached to each IP packet. The SDIO control data may define one or more control registers. These control registers may be read prior to initiating the data transfer. In one embodiment, the control registers may determine whether the SDIO client has pending data that should be read, or, the control register read may be a check to determine that the client has enough buffer space to initiate a write transfer from the SDCC host. Since a transfer of each IP packet may currently require an attachment of this overhead control information, if the amount of overhead for each IP packet is decreased, the space previously contained by the control information can be replaced with additional IP packet data, thereby increasing the overall IP data transfer rate.
A related issue is the amount of AP CPU overhead associated with each SDIO transfer. In an upload transfer from the SDCC host to the SDIO client, a Direct Memory Access (DMA) may be implemented by SDCC hardware in order to move the data from the system memory to the SDCC hardware. The data would then be sent over the SDIO interface bus to the SDIO client. In such an operation, a SDCC driver is typically used to program the DMA operation—relinquishing the CPU for other processing needs. The SDCC hardware then typically notifies the driver software of the completion of the DMA operation asynchronously by interrupting the CPU. Therefore, the time lost from the CPU interrupt must be more than offset by the CPU gains in using the DMA operation. Otherwise, there would be lower CPU overhead lost with using the CPU to transfer the data instead of using the DMA.
For example, when each IP packet is transferred in a single transaction, the DMA transfer is small and of the order of 1500 bytes (assuming Ethernet MTU). When this occurs, the rate at which the host CPU needs to process interrupts limits the ability to transfer data at a very high data rate. Similarly, in downlink transfers from the SDIO client to the SDCC host, an additional host CPU interrupt occurs as the SDIO client notifies the SDCC host that data is available to be transmitted through the use of an interrupt, which is necessary because of the asymmetric nature of the SDIO protocol (the host must initiate all transfers). Upon receiving the interrupt, the SDCC host would start a read operation to read the available data from the SDIO client. Decreasing the number of AP host interrupts per IP packet would increase the rate at which packets are transferred.